CVE-2025-563017.5HighCWE-1281

CVE-2025-56301: Chipsalliance Rocket-Chip vulnerability

Chipsalliance · Rocket-Chip

Affected: Chipsalliance Rocket-Chip · Exploitation: unlikely (under 1%)

Not in CyberSIXT coverage yet: no article names this CVE. This page shows the public record.

0.6%probability of exploitation in the next 30 days

51st percentile

050100

Higher than 51% of scored CVEs

7.5HighCVSS 3.1

LowMediumHighCrit.

DescriptionCVE.org

An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.

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Exploitation: Unlikely (under 1%). EPSS under 1%, or no score yet.
CISA KEV: Not listed
Public check: No public nuclei template
Weakness: Sequence of Processor Instructions Leads to Unexpected Behavior · Other weaknesses
Published: September 2025
Band: Unlikely (under 1%), September 2025

CoverageNo articles yet

No CyberSIXT article names CVE-2025-56301 yet, so there is no coverage timeline, action brief or change log for it. Everything on this page comes from the public CVE record, CISA KEV, EPSS and the nuclei template index. Search the archive or see the CVEs in the news.